The inventive concept relates to a bonding pad structure of a semiconductor device and to a method of manufacturing a bonding pad structure.
An integrated circuit of a semiconductor device is often electrically connected to an external device, circuitry, etc. by a wire. To this end, the wire is bonded to a bonding pad of the semiconductor device. The process of bonding the wire to the bonding pad mainly entails exerting a mechanical compressive force on the wire. This force is applied to the wire, and hence to the bonding pad, by a mechanical bonding apparatus. In general, the bonding pad includes a substrate, an upper wiring layer to which the wire is bonded, an interlayer insulation layer interposed between the upper wiring layer and the substrate, and at least one lower wiring layer embedded in the interlayer insulation layer.
The layout of the lower wiring layer(s) has been influenced by recent demands for smaller and smaller semiconductor devices. In particular, the interlayer insulation layer and the lower wiring layer(s) are becoming thinner as semiconductor devices are being scaled down. As a result, stress from the outside of the device has a relatively high chance of causing the bonding pad to crack. Specifically, the interlayer insulation layer tends to crack just below the upper wiring layer when the compressive force generated during a wire bonding process is applied to the bonding pad. This is especially prevalent in the case in which the interlay insulation layer is mainly formed of silicon oxide. Silicon oxide does not adhere well to metal and thus, the interlayer insulation layer of the bonding pad is likely to crack at its boundary with the upper wiring layer. In this case, the upper wiring layer can peel off of the interlayer insulation layer, i.e., a so-called peel-off defect occurs.